This invention relates to digital memories; and more particularly to, static digital memories on a semiconductor substrate.
Basically, static semiconductor memories are defined as those memories wherein stored information will remain indefinitely without the aid of any "refresh cycles", so long as power is supplied to the memory. By comparison, dynamic semiconductor memories must be refreshed periodically; otherwise, the information stored in the memories will dissipate. Typically, the refresh rate for a dynamic semiconductor memory is on the order of several hundred times per second.
Thus, since static semiconductor memories require no refresh cycles (and no associated control circuitry), they are often preferred over dynamic memories as the storage means in many digital systems. However, static semiconductor memories typically require more physical space for their layout on a semiconductor chip than do dynamic memories. Accordingly, a disadvantage of the static semiconductor memory is that the number of static memory cells per chip is generally less than the number of dynamic memory cells per chip.
To overcome this problem, both the number of components per static memory cell and the number of interconnections between the cells must be minimized. However, in the past, a single static memory cell typically included at least six components, and had at least five interconnecting nodes between cells. These will subsequently be pointed out in conjunction with the description of FIG. 2. Dynamic memories, by comparison, typically include only two components per cell (a storage capacitor and a transfer gate); and have only three interconnecting nodes per cell (one node for connection to a bit line, one node for connection to a word line, and one node for connection to a supply voltage bus).
Accordingly, a primary object of this invention is to provide a static semiconductor memory having a reduced number of components and interconnections per cell over the prior art.